0.18 lm CMOS backplane receiver with decision-feedback equalisation embedded

Introduction: The speed of serial links across copper backplanes has seen a steady rise over recent years. As data rates increase, transmission suffers from severe eye closure caused by intersymbol interference (ISI) owing to high-frequency attenuation of the copper traces drawn on PCBs, crosstalk noise between connector pins, and reflections that occur as data rates move into the microwave frequency range of operation and beyond. Feed-forward equalisation (FFE) is effective in counteracting ISI but unsuitable for some legacy backplanes with significant high-frequency crosstalk since they amplify high-frequency noise. PAM-4 alternatives alleviate ISI but have interoperability issues and suffer from reduced voltage margins that exacerbate crosstalk effects. Decision-feedback equalisation (DFE) [1–3] can overcome the drawback of high-frequency noise amplification. DFE uses clean decisions of previously received symbols to remove ISI in the current symbol. Since it does not boost highfrequency noise such as crosstalk or wideband noise to equalise the channel, this technique can be suitable for backplane environments with high channel count. An RX clock signal is needed for delaying the currently received data to obtain prior data decision. In [2] a PLL block is used to generate multiphase clocks. The RX uses the PLL clock as an initial guess for the incoming data phase and frequency. The exact phase and frequency at the RX is recovered from the data by a digital clock and data recovery loop architecture. In [3] the FFE without DFE opens the input data eye enough to permit the CDR to achieve lock and thus obtain the clock information for DFE later operation. In this Letter, a referenceless CDR architecture is adopted and the DFE circuit is embedded in the PFD design of the CDR circuit, enabling clock recovery and DFE operation concurrently.